This article mainly explains MIPS-based PIC32MM series of 32-bit microcontrollers, first introduced the MIPS32 bit architecture, followed by the introduction of the PIC32MM series of main features and PIC32MM series of analog integration, and finally elaborated the PIC32MM series of target applications, follow the specific details of the small series to understand .
MIPS IntroductionMIPS is a very popular RISC processor in the world. MIPS stands for "Microprocessor without interlocked piped stages". The mechanism is to use software methods to avoid data-related problems in the pipeline. It was first developed in the early 1980s by a team led by Professor Hennessy at Stanford University. MIPS's R series is a microprocessor for RISC industrial products developed on this basis. These series of products are used by many computer companies to construct various workstations and computer systems. MIPS is one of the earliest commercial RISC architecture chips. The new architecture integrates all the original MIPS instruction set and adds many more powerful features.
MIPS32 bit architecture detailedThe MIPS32® architecture refreshes the performance standard of 32-bit embedded processors. It is the foundation of MIPS Technologies' next-generation, high-performance MIPS-BasedTM processor SoC roadmap and is upwardly compatible with the MIPS64® 64-bit architecture. The MIPS architecture has a powerful instruction set, scalability from 32-bit to 64-bit, extensive software development tools, and support from numerous MIPS Technologies licensees, leading the embedded architecture. The MIPS32 architecture is a superset of the previous MIPS ITM and MIPS IITM instruction set architecture (ISA), incorporating powerful new instructions specifically for embedded applications, and the previous only 64-bit R4000TM and R5000® MIPS® Verified memory management and privileged mode control mechanisms that can be seen in the processor. By integrating powerful new features, standardizing privileged mode instructions, and supporting previous-generation ISAs, the MIPS32 architecture provides a solid high-performance foundation for all future 32-bit MIPS-based development.
The MIPS32 architecture is based on a fixed-length, regularly coded instruction set and uses a load/store data model. Improved, this architecture supports optimized execution of high-level languages. Its arithmetic and logic operations take the form of three operands, allowing the compiler to optimize complex expressions. In addition, it comes with 32 general-purpose registers that allow the compiler to further optimize code generation performance by maintaining frequent access to the data in the registers.
The MIPS32 architecture derives privileged mode exception handling and memory management from popular R4000/R5000 class 64-bit processors. It uses a set of registers to reflect the configuration of the cache, MMU, TLB, and other privileged functions implemented in each core. By standardizing privileged mode and memory management, and providing information via configuration registers, the MIPS32 architecture enables real-time operating systems, other development tools, and application code to be executed simultaneously and reused across the MIPS32 and MIPS64 processor families. .
Its high-performance cache and memory management solutions continue to be a major advantage of the MIPS architecture. The MIPS32 architecture further extends this advantage with well-defined cache control options. Instruction and data buffer sizes can range from 256 bytes to 4 Mbytes. The data cache can use write-back or write-through policies. No cache is also an optional configuration. Memory management mechanisms can use TLB or Block Address Translation (BAT) strategies. With TLB, the MIPS32 architecture meets the memory management requirements of Windows CE and Linux.
With the addition of intensive data processing, data flow, and predicated operaTIons, the growing computing needs of the embedded market can be met. CondiTIonal data move and data cache prefetch instructions were introduced to increase data throughput for communication and multimedia applications. Fixed floating point DSP instructions can further enhance multimedia processing capabilities. These new instructions, including multiplication, multiply-add, multiply-subtract, and "count leading 0s/1s," provide additional processing power for audio, video, and multimedia without the need for additional DSP hardware in the system. High performance. Powerful floating-point instructions can speed up the execution of certain tasks, such as the processing of some DSP algorithms and the real-time calculation of graphics operations. Floating-point operation can choose software simulation. Finally, to simplify system integration tasks, the MIPS32 standard defines EJTAG (Enhanced JTAG) option functions as a non-intrusive, on-chip real-time debugging system.
The PIC32MM family is Microchip's lowest power and most cost-effective 32-bit PIC32 microcontroller family. The PIC32MM family fills the gap between our popular PIC24F XLP and PIC32MX families. PIC32MM devices sleep mode current as low as 500 nA, package size as small as 4 & TImes; 4 mm, suitable for applications that require longer battery life and smaller form factor. These devices have core-independent peripherals such as configurable logic cells (CLC) and multiple output capture/compare/PWM (MCCP) designed to reduce CPU load. With a compact microMIPSTM instruction, a microApTIvTM UC core, and a shadow register set, the PIC32MM family can achieve 79 CoreMarkTM scores at 25 MHz. microMIPSISA incorporates 16-bit and 32-bit instructions for compact code. Microchip's MPLAB® Code Configurator (MCC) supports this family of devices, helping to simplify the design.
PIC32MM series main features1, low power consumption: optimize the battery power performance
2, low voltage sleep mode, RAM data retention current "500 nA
3, low cost: unit price as low as 0.60 US dollars in bulk purchase
Small package: 4 × 4 mm, 5 × 5 mm and 6 × 6 mm
5ã€Integrate core-independent peripherals
6, ADC, comparator, RTCC, WDT and CLC
7. Flexible PWM/IC/OC/Timer (MCCP and SCCP)
PIC32MM Series Analog Integration1, 12-bit 200 ksps ADC, 5-bit DAC and Comparator
2. Supported by MPLAB code configurator to simplify setup
1, low power / wireless applications:
• IoT sensor node
• Networked thermostat/environmental monitoring
• Portable medical equipment and remote control
2, consumer applications:
• Game Consoles and Home Health/Fitness Equipment
3, industrial control applications:
• Building Automation and Temperature/Lighting Control
4, low-cost motor control applications:
• White appliances and small appliances
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