If parallelism is compared to multi-lane highways, serial technology is at best a trail between mountains. The parallel port (Standard Parall el Port) can transmit information through 8 data lines at the same time, one byte at a time. The serial port (commonly known as COM port) can only transmit data with 1 line, one bit at a time. When the parallel port completes the word "advanced" transfer once and for all, the serial port is still busy transmitting its initial "a".
However, industries that are constantly chasing the latest technology are moving from traditional parallel standards to new high-speed serial interface technologies, from IEEE1284 to USB, from PATA to SATA, from PCI to PCI Express...
These seemingly contradictory changes affect all aspects of the industry chain, including packaging, board level and even the entire system design, but also quietly set off a revolution in high-speed serial testing technology.
Exploring the Way of "Transformation"
Taking the computer bus as an example, the speed can be described as ever-changing. As a "cart" for transferring data between the host computer and external devices, the bus and the interface naturally pursue higher and faster speeds. At the same time, the parallel port has been the preferred connection method for printers for more than a decade. But the emergence of laser printers broke this "monopoly." When the Epson 6200L prints 2MB images, the speed difference is not too big; but when the picture is increased to 7.5MB, it takes 18 seconds to use the USB interface and 33 seconds to use the parallel port from clicking "Print" to final output. It can be seen that the parallel port is already insufficient for the popular laser printer.
Development of PC bus
Admittedly, parallel technology has always been an important means to increase speed, but its further development has encountered obstacles. First, because the premise of the parallel transmission mode is to use the same timing to propagate the signal and receive the signal with the same timing, and excessively raising the clock frequency will make it difficult to match the timing of the data transmission with the clock. The wiring length is slightly different, and the data will be different from the clock. The timing is delivered. In addition, increasing the clock frequency is also likely to cause interference between signal lines, resulting in transmission errors. Therefore, it is difficult to achieve high speed in the parallel mode. In terms of manufacturing cost, increasing the bit width will undoubtedly lead to an increase in the number of wiring on the motherboard and the expansion board, and the cost will increase.
Unlike the parallel standard to be replaced, most of the new serial standards are based on clock embedded systems, which means that the clock signal will not accompany the data from one end of the connection to the other, which means that the clock signal must be The receiving end is accurately recovered along with the data signal. These systems do not have an expansion cap and do not encounter timing and calibration bottlenecks at higher bandwidths like parallel standards. More and more designers are trying to apply high-speed serial technology to their designs, but technological changes have also brought new challenges.
Six major challenges
Traditional data buses (such as IDE parallel ports) have long been replaced by high-speed serial buses, such as the development of mature PCIe, SATA, etc., the transmission speed has also changed a lot. For example, the second-generation PCIe transmission speed is as high as 5Gb/s, while the third generation of SATA is as high as 6Gb/s, and faster bus technology is currently under discussion.
The dramatic increase in speed has increased the complexity of the technology, while industry norms and standards have become more widespread. The earliest high-speed serial bus standard was the USB 2.0 introduced in 2000. Its communication speed is 480Mbps, which requires mandatory testing before it can be designed, produced, shipped and labeled with USBLogo. However, many bus standards such as DisplayPort, SATA, and PCI Express are not mandatory, and high-speed serial buses have been widely deployed.
USB evolution
These changes require engineers to ensure that their designs are tested in the shortest possible time and efficiently. Among them, efficiency includes two aspects: production efficiency and economic efficiency. Today, when product time-to-market is becoming more and more urgent, efficiency may sometimes determine the survival of a product. This is especially true for high-speed serial testing:
First, the speed increase makes the design margin (fault-tolerant margin) change. For example, when the speed is 100Mbps, it corresponds to 10 nanoseconds. If the design technique, skill and test scheme are not very good, the error corresponds to 1 nanosecond. It is 1/10 and the product can pass. But when the speed is increased to 1 Gbps, it corresponds to 1 nanosecond. If the test technology and scheme stay at 1 nanosecond, the proportion of errors is 50%. Half of the errors are of course fatal. Obviously, the old technology and methods make the space for making mistakes less.
Second, the efficient test plan requires high precision and high efficiency of the test, grasping the problem and providing the corresponding solution to find the underlying cause. Perhaps for the user, computer restart is just a bad experience. But the company that produces the computer will find the problem through the test plan and avoid it in the next stage. Tektronix introduced new TLA7S16 and TLA7S08 serial analyzers for testing and validating PCIe 1.0 and 2.0 designs in September 2007, providing detailed PCIe 2.0 protocol information and cross-bus analysis capabilities to see three layers of conditions. , namely the physical layer, the data link layer, and the transaction layer. If the command sent is to take the number 2, but takes the number 1, this development error can be seen by many protocol analyzers. But where is the root of the change from 2 to 1? Tektronix's solution is to be able to connect, map, and see that 2 becomes 1 in the data layer, and then find the root of 2 to 1 in the physical layer. These root causes may be bit errors (such as overshoot), poor management, or reflections on the board's board design. In this way, the engineer can change the board, line width and line spacing according to his own experience.
Finally, the device has reached the speed of 3G, 6G, or even 10G. It is true that 20G is better than 10G. "But in addition to the indicators, it depends on how many things 20G and 10G do. The figures may be a view of selling or comparing shallow customers to the instrument," Sun Zhiqiang said. Tektronix saw the impact of engineers behind the numbers and aims to meet customer requirements through its full range of hardware metrics.
USB evolution
These changes require engineers to ensure that their designs are tested in the shortest possible time and efficiently. Among them, efficiency includes two aspects: production efficiency and economic efficiency. Today, when product time-to-market is becoming more and more urgent, efficiency may sometimes determine the survival of a product. This is especially true for high-speed serial testing:
First, the speed increase makes the design margin (fault-tolerant margin) change. For example, when the speed is 100Mbps, it corresponds to 10 nanoseconds. If the design technique, skill and test scheme are not very good, the error corresponds to 1 nanosecond. It is 1/10 and the product can pass. But when the speed is increased to 1 Gbps, it corresponds to 1 nanosecond. If the test technology and scheme stay at 1 nanosecond, the proportion of errors is 50%. Half of the errors are of course fatal. Obviously, the old technology and methods make the space for making mistakes less.
Second, the efficient test plan requires high precision and high efficiency of the test, grasping the problem and providing the corresponding solution to find the underlying cause. Perhaps for the user, computer restart is just a bad experience. But the company that produces the computer will find the problem through the test plan and avoid it in the next stage. Tektronix introduced new TLA7S16 and TLA7S08 serial analyzers for testing and validating PCIe 1.0 and 2.0 designs in September 2007, providing detailed PCIe 2.0 protocol information and cross-bus analysis capabilities to see three layers of conditions. , namely the physical layer, the data link layer, and the transaction layer. If the command sent is to take the number 2, but takes the number 1, this development error can be seen by many protocol analyzers. But where is the root of the change from 2 to 1? Tektronix's solution is to be able to connect, map, and see that 2 becomes 1 in the data layer, and then find the root of 2 to 1 in the physical layer. These root causes may be bit errors (such as overshoot), poor power management, or reflections on the board design. In this way, the engineer can change the board, line width and line spacing according to his own experience.
Finally, the test instrument has reached the speed of 3G, 6G, or even 10G. It is true that 20G is better than 10G. "But in addition to the indicators, it depends on how many things 20G and 10G do. The figures may be a view of selling or comparing shallow customers to the instrument," Sun Zhiqiang said. Tektronix saw the impact of engineers behind the numbers and aims to meet customer requirements through its full range of hardware metrics.
USB evolution
These changes require engineers to ensure that their designs are tested in the shortest possible time and efficiently. Among them, efficiency includes two aspects: production efficiency and economic efficiency. Today, when product time-to-market is becoming more and more urgent, efficiency may sometimes determine the survival of a product. This is especially true for high-speed serial testing:
First, the speed increase makes the design margin (fault-tolerant margin) change. For example, when the speed is 100Mbps, it corresponds to 10 nanoseconds. If the design technique, skill and test scheme are not very good, the error corresponds to 1 nanosecond. It is 1/10 and the product can pass. But when the speed is increased to 1 Gbps, it corresponds to 1 nanosecond. If the test technology and scheme stay at 1 nanosecond, the proportion of errors is 50%. Half of the errors are of course fatal. Obviously, the old technology and methods make the space for making mistakes less.
Second, the efficient test plan requires high precision and high efficiency of the test, grasping the problem and providing the corresponding solution to find the underlying cause. Perhaps for the user, computer restart is just a bad experience. But the company that produces the computer will find the problem through the test plan and avoid it in the next stage. Tektronix introduced new TLA7S16 and TLA7S08 serial analyzers for testing and validating PCIe 1.0 and 2.0 designs in September 2007, providing detailed PCIe 2.0 protocol information and cross-bus analysis capabilities to see three layers of conditions. , namely the physical layer, the data link layer, and the transaction layer. If the command sent is to take the number 2, but takes the number 1, this development error can be seen by many protocol analyzers. But where is the root of the change from 2 to 1? Tektronix's solution is to be able to connect, map, and see that 2 becomes 1 in the data layer, and then find the root of 2 to 1 in the physical layer. These root causes may be bit errors (such as overshoot), poor power management, or reflections on the board design. In this way, the engineer can change the board, line width and line spacing according to his own experience.
Finally, the test instrument has reached the speed of 3G, 6G, or even 10G. It is true that 20G is better than 10G. "But in addition to the indicators, it depends on how many things 20G and 10G do. The figures may be a view of selling or comparing shallow customers to the instrument," Sun Zhiqiang said. Tektronix saw the impact of engineers behind the numbers and aims to meet customer requirements through its full range of hardware metrics.
USB evolution
These changes require engineers to ensure that their designs are tested in the shortest possible time and efficiently. Among them, efficiency includes two aspects: production efficiency and economic efficiency. Today, when product time-to-market is becoming more and more urgent, efficiency may sometimes determine the survival of a product. This is especially true for high-speed serial testing:
First, the speed increase makes the design margin (fault-tolerant margin) change. For example, when the speed is 100Mbps, it corresponds to 10 nanoseconds. If the design technique, skill and test scheme are not very good, the error corresponds to 1 nanosecond. It is 1/10 and the product can pass. But when the speed is increased to 1 Gbps, it corresponds to 1 nanosecond. If the test technology and scheme stay at 1 nanosecond, the proportion of errors is 50%. Half of the errors are of course fatal. Obviously, the old technology and methods make the space for making mistakes less.
Second, the efficient test plan requires high precision and high efficiency of the test, grasping the problem and providing the corresponding solution to find the underlying cause. Perhaps for the user, computer restart is just a bad experience. But the company that produces the computer will find the problem through the test plan and avoid it in the next stage. Tektronix introduced new TLA7S16 and TLA7S08 serial analyzers for testing and validating PCIe 1.0 and 2.0 designs in September 2007, providing detailed PCIe 2.0 protocol information and cross-bus analysis capabilities to see three layers of conditions. , namely the physical layer, the data link layer, and the transaction layer. If the command sent is to take the number 2, but takes the number 1, this development error can be seen by many protocol analyzers. But where is the root of the change from 2 to 1? Tektronix's solution is to be able to connect, map, and see that 2 becomes 1 in the data layer, and then find the root of 2 to 1 in the physical layer. These root causes may be bit errors (such as overshoot), poor power management, or reflections on the board design. In this way, the engineer can change the board, line width and line spacing according to his own experience.
Finally, the test instrument has reached the speed of 3G, 6G, or even 10G. It is true that 20G is better than 10G. "But in addition to the indicators, it depends on how many things 20G and 10G do. The figures may be a view of selling or comparing shallow customers to the instrument," Sun Zhiqiang said. Tektronix saw the impact of engineers behind the numbers and aims to meet customer requirements through its full range of hardware metrics.
It can be asserted that in the future electronic information industry, high-speed serial bus must be the mainstream of speed transmission solutions. Since 2006, Tektronix has been promoting a number of "digital new world" strategies, the most important of which is high-speed serial testing. Sun Zhiqiang, D&M market development manager for Tektronix Asia Pacific, said that there are six challenges in high-speed serial testing, namely signal integrity, receiver testing, serial data network and link analysis, compliance testing, system integration and data link analysis.
From production, high-speed serial testing can be divided into three parts: design, commissioning and inspection, and conformance testing. In the design phase, engineers can use the relevant simulation software to evaluate their own designs; and the real meaning of testing begins with the second phase, engineers need to use a variety of instruments to debug and test the system; at the same time, in order to meet the specifications of an application Conformance testing is also essential to achieve barrier-free interconnection of products between various manufacturers. However, because the conformance test belongs to the verification process, it can only measure whether the indicator meets the requirements, and cannot provide the fault and the improvement, so it cannot replace the debugging process.
From the perspective of the entire system, high-speed serial testing can be divided into: source, receiver and interconnect testing. The source test is a description of the source of the high-speed serial bus. It is usually measured by various indicators such as jitter, eye diagram and level. The receiver test is more about the receiver's receiving capability. The interconnect is more concerned. Connect the source and receiver traces, and other media characteristics (including impedance and crosstalk, etc.).
Six major challenges
Signal integrity is for source-side testing. The test specifications for each serial bus source are different, but the main considerations are basically the same. Among all the parameters, jitter and time offset are almost the same for all standards. An eye diagram is a method of characterizing the macroscopic characteristics of a serial signal, looking at the intersection of the transmission quality of the signal and the upper and lower deformations. The requirements for the eye diagram are just like the human eye. It should be clean and beautiful, that is, the upper and lower deformation noise should be small, the finer the better, the smaller the jitter.
Conformance testing is a bit like a "stamped" test. It is a test after the other five aspects are done to ensure that the interface can connect to any standard interface device in the world.
Serial data networks and links include impedance and link analysis of serial data network boards. The ideal impedance is a constant. For example, when light travels, the air does not reflect or refract, but through the window, it refracts and reflects. High-speed serial is typically a 100 ohm serial impedance, but if done poorly, it is 85 ohms or 82 ohms. In addition, comprehensive serial link analysis of noise and jitter is required. According to Sun Zhiqiang, Tektronix is ​​the only and the first to provide complete serial data link analysis on sampling oscilloscopes while observing jitter noise and bit errors.
"Two or three years ago, we didn't care about receiver testing," Sun Zhiqiang told Electronic Engineering World. Because Tektronix believes that the transmitter is tested well, the margins behind it are sufficient to make the signal received by the receiver intact. However, with the increase of speed and complexity, many signals of 1 become 0.8, 0.9 or even 0.7 at the receiving end, and once it becomes 0.5, it is impossible to determine whether the transmitted signal is 1 or 0, so high-speed serial test. Includes receiver testing. This requires the test instrument not only to be convenient to use, but also to generate as many error signals as possible and deliberately issued to judge the performance of the receiver. Traditional receiver testing often requires many sources such as noise sources, jitter sources, and basic data sources.
The four major challenges mentioned earlier exist in the physical layer, and the challenges of the data link layer come from two aspects: system integration and data link analysis. If the physical layer is good in all four aspects, you need to check the data link layer. This requires not only the performance of the test instrument, but also the multi-layer observation, that is, the oscilloscope (see physical layer) and the logic analyzer (see The data layer) is linked to a piece, and Tektronix introduced this concept five or six months ago. The physical layer mainly sees the physical analysis and simulation analysis of the serial link, while the data link layer mainly analyzes the data and protocols. The TAK7S16 and TLA7S08 serial analyzers introduced by Tektronix in September 2007 are implemented. An ideal cycle from equipment to test to design.
Of course, the six major challenges of high-speed serial testing are the customer's problems and challenges in the development process, which can be quickly resolved; and there are early preparations for problems that may be encountered tomorrow or the day after tomorrow. Rather than the challenge of engineers, it is the challenge of the test company, and the challenge of the test company comes from the challenge of using test instruments. Sun Zhiqiang said that Tektronix aims to help testers achieve easier design and production. , the concept of "Enabling" often mentioned in recent years.
How to meet the final needs
If you look for a typical application for high-speed serial technology, you can find it with a typical computer system. Such as PCI Express, HDMI3D, DisplayPort, SATA2 generation 3 generation, USB3.0, etc., applications such as high-speed DVR, communication, 10G Ethernet and so on. Sun Zhiqiang said that Tektronix's mission is to cooperate well with the organization and core companies of these programs.
The difference between applications and standards determines the different needs of customers. So how do high-speed serial test systems, which are already very complex, meet these diverse needs?
Testing needs of test centers, system vendors, modules, and chip vendors are the same - time is efficient, but the focus is not the same, so the choice of instruments is not the same. Production companies are more concerned with price, because time is money, and also requires test equipment to do 10 minutes in 1 minute. For example, the Tektronix DPO Series oscilloscope can take 100 seconds to capture 100 waveforms, while the DSO (Digital Storage Oscilloscope) series can take 60 seconds or 2 minutes. Efficiency, fairness, reliability, and repeatability are critical to the test center. If the same test process, the same personnel test, the test results of the instrument at 8 o'clock in the morning and 2 o'clock in the afternoon are different, which means that the temperature has a great influence on the instrument and the repeatability is not high. The requirements for system chips and module manufacturers are different.
A variety of needs are driving the advancement of technology, and no technology has an absolute competitive advantage. From the initial serial to the subsequent parallel, to the current high-speed serial, however, the basic principle of "higher parallel communication at the same frequency" is no problem. So how many challenges are there after the "six major challenges"? And let us wait and see!
However, industries that are constantly chasing the latest technology are moving from traditional parallel standards to new high-speed serial interface technologies, from IEEE1284 to USB, from PATA to SATA, from PCI to PCI Express...
These seemingly contradictory changes affect all aspects of the industry chain, including packaging, board level and even the entire system design, but also quietly set off a revolution in high-speed serial testing technology.
Exploring the Way of "Transformation"
Taking the computer bus as an example, the speed can be described as ever-changing. As a "cart" for transferring data between the host computer and external devices, the bus and the interface naturally pursue higher and faster speeds. At the same time, the parallel port has been the preferred connection method for printers for more than a decade. But the emergence of laser printers broke this "monopoly." When the Epson 6200L prints 2MB images, the speed difference is not too big; but when the picture is increased to 7.5MB, it takes 18 seconds to use the USB interface and 33 seconds to use the parallel port from clicking "Print" to final output. It can be seen that the parallel port is already insufficient for the popular laser printer.
Development of PC bus
Admittedly, parallel technology has always been an important means to increase speed, but its further development has encountered obstacles. First, because the premise of the parallel transmission mode is to use the same timing to propagate the signal and receive the signal with the same timing, and excessively raising the clock frequency will make it difficult to match the timing of the data transmission with the clock. The wiring length is slightly different, and the data will be different from the clock. The timing is delivered. In addition, increasing the clock frequency is also likely to cause interference between signal lines, resulting in transmission errors. Therefore, it is difficult to achieve high speed in the parallel mode. In terms of manufacturing cost, increasing the bit width will undoubtedly lead to an increase in the number of wiring on the motherboard and the expansion board, and the cost will increase.
Unlike the parallel standard to be replaced, most of the new serial standards are based on clock embedded systems, which means that the clock signal will not accompany the data from one end of the connection to the other, which means that the clock signal must be The receiving end is accurately recovered along with the data signal. These systems do not have an expansion cap and do not encounter timing and calibration bottlenecks at higher bandwidths like parallel standards. More and more designers are trying to apply high-speed serial technology to their designs, but technological changes have also brought new challenges.
Six major challenges
Traditional data buses (such as IDE parallel ports) have long been replaced by high-speed serial buses, such as the development of mature PCIe, SATA, etc., the transmission speed has also changed a lot. For example, the second-generation PCIe transmission speed is as high as 5Gb/s, while the third generation of SATA is as high as 6Gb/s, and faster bus technology is currently under discussion.
The dramatic increase in speed has increased the complexity of the technology, while industry norms and standards have become more widespread. The earliest high-speed serial bus standard was the USB 2.0 introduced in 2000. Its communication speed is 480Mbps, which requires mandatory testing before it can be designed, produced, shipped and labeled with USBLogo. However, many bus standards such as DisplayPort, SATA, and PCI Express are not mandatory, and high-speed serial buses have been widely deployed.
USB evolution
These changes require engineers to ensure that their designs are tested in the shortest possible time and efficiently. Among them, efficiency includes two aspects: production efficiency and economic efficiency. Today, when product time-to-market is becoming more and more urgent, efficiency may sometimes determine the survival of a product. This is especially true for high-speed serial testing:
First, the speed increase makes the design margin (fault-tolerant margin) change. For example, when the speed is 100Mbps, it corresponds to 10 nanoseconds. If the design technique, skill and test scheme are not very good, the error corresponds to 1 nanosecond. It is 1/10 and the product can pass. But when the speed is increased to 1 Gbps, it corresponds to 1 nanosecond. If the test technology and scheme stay at 1 nanosecond, the proportion of errors is 50%. Half of the errors are of course fatal. Obviously, the old technology and methods make the space for making mistakes less.
Second, the efficient test plan requires high precision and high efficiency of the test, grasping the problem and providing the corresponding solution to find the underlying cause. Perhaps for the user, computer restart is just a bad experience. But the company that produces the computer will find the problem through the test plan and avoid it in the next stage. Tektronix introduced new TLA7S16 and TLA7S08 serial analyzers for testing and validating PCIe 1.0 and 2.0 designs in September 2007, providing detailed PCIe 2.0 protocol information and cross-bus analysis capabilities to see three layers of conditions. , namely the physical layer, the data link layer, and the transaction layer. If the command sent is to take the number 2, but takes the number 1, this development error can be seen by many protocol analyzers. But where is the root of the change from 2 to 1? Tektronix's solution is to be able to connect, map, and see that 2 becomes 1 in the data layer, and then find the root of 2 to 1 in the physical layer. These root causes may be bit errors (such as overshoot), poor management, or reflections on the board's board design. In this way, the engineer can change the board, line width and line spacing according to his own experience.
Finally, the device has reached the speed of 3G, 6G, or even 10G. It is true that 20G is better than 10G. "But in addition to the indicators, it depends on how many things 20G and 10G do. The figures may be a view of selling or comparing shallow customers to the instrument," Sun Zhiqiang said. Tektronix saw the impact of engineers behind the numbers and aims to meet customer requirements through its full range of hardware metrics.
USB evolution
These changes require engineers to ensure that their designs are tested in the shortest possible time and efficiently. Among them, efficiency includes two aspects: production efficiency and economic efficiency. Today, when product time-to-market is becoming more and more urgent, efficiency may sometimes determine the survival of a product. This is especially true for high-speed serial testing:
First, the speed increase makes the design margin (fault-tolerant margin) change. For example, when the speed is 100Mbps, it corresponds to 10 nanoseconds. If the design technique, skill and test scheme are not very good, the error corresponds to 1 nanosecond. It is 1/10 and the product can pass. But when the speed is increased to 1 Gbps, it corresponds to 1 nanosecond. If the test technology and scheme stay at 1 nanosecond, the proportion of errors is 50%. Half of the errors are of course fatal. Obviously, the old technology and methods make the space for making mistakes less.
Second, the efficient test plan requires high precision and high efficiency of the test, grasping the problem and providing the corresponding solution to find the underlying cause. Perhaps for the user, computer restart is just a bad experience. But the company that produces the computer will find the problem through the test plan and avoid it in the next stage. Tektronix introduced new TLA7S16 and TLA7S08 serial analyzers for testing and validating PCIe 1.0 and 2.0 designs in September 2007, providing detailed PCIe 2.0 protocol information and cross-bus analysis capabilities to see three layers of conditions. , namely the physical layer, the data link layer, and the transaction layer. If the command sent is to take the number 2, but takes the number 1, this development error can be seen by many protocol analyzers. But where is the root of the change from 2 to 1? Tektronix's solution is to be able to connect, map, and see that 2 becomes 1 in the data layer, and then find the root of 2 to 1 in the physical layer. These root causes may be bit errors (such as overshoot), poor power management, or reflections on the board design. In this way, the engineer can change the board, line width and line spacing according to his own experience.
Finally, the test instrument has reached the speed of 3G, 6G, or even 10G. It is true that 20G is better than 10G. "But in addition to the indicators, it depends on how many things 20G and 10G do. The figures may be a view of selling or comparing shallow customers to the instrument," Sun Zhiqiang said. Tektronix saw the impact of engineers behind the numbers and aims to meet customer requirements through its full range of hardware metrics.
USB evolution
These changes require engineers to ensure that their designs are tested in the shortest possible time and efficiently. Among them, efficiency includes two aspects: production efficiency and economic efficiency. Today, when product time-to-market is becoming more and more urgent, efficiency may sometimes determine the survival of a product. This is especially true for high-speed serial testing:
First, the speed increase makes the design margin (fault-tolerant margin) change. For example, when the speed is 100Mbps, it corresponds to 10 nanoseconds. If the design technique, skill and test scheme are not very good, the error corresponds to 1 nanosecond. It is 1/10 and the product can pass. But when the speed is increased to 1 Gbps, it corresponds to 1 nanosecond. If the test technology and scheme stay at 1 nanosecond, the proportion of errors is 50%. Half of the errors are of course fatal. Obviously, the old technology and methods make the space for making mistakes less.
Second, the efficient test plan requires high precision and high efficiency of the test, grasping the problem and providing the corresponding solution to find the underlying cause. Perhaps for the user, computer restart is just a bad experience. But the company that produces the computer will find the problem through the test plan and avoid it in the next stage. Tektronix introduced new TLA7S16 and TLA7S08 serial analyzers for testing and validating PCIe 1.0 and 2.0 designs in September 2007, providing detailed PCIe 2.0 protocol information and cross-bus analysis capabilities to see three layers of conditions. , namely the physical layer, the data link layer, and the transaction layer. If the command sent is to take the number 2, but takes the number 1, this development error can be seen by many protocol analyzers. But where is the root of the change from 2 to 1? Tektronix's solution is to be able to connect, map, and see that 2 becomes 1 in the data layer, and then find the root of 2 to 1 in the physical layer. These root causes may be bit errors (such as overshoot), poor power management, or reflections on the board design. In this way, the engineer can change the board, line width and line spacing according to his own experience.
Finally, the test instrument has reached the speed of 3G, 6G, or even 10G. It is true that 20G is better than 10G. "But in addition to the indicators, it depends on how many things 20G and 10G do. The figures may be a view of selling or comparing shallow customers to the instrument," Sun Zhiqiang said. Tektronix saw the impact of engineers behind the numbers and aims to meet customer requirements through its full range of hardware metrics.
USB evolution
These changes require engineers to ensure that their designs are tested in the shortest possible time and efficiently. Among them, efficiency includes two aspects: production efficiency and economic efficiency. Today, when product time-to-market is becoming more and more urgent, efficiency may sometimes determine the survival of a product. This is especially true for high-speed serial testing:
First, the speed increase makes the design margin (fault-tolerant margin) change. For example, when the speed is 100Mbps, it corresponds to 10 nanoseconds. If the design technique, skill and test scheme are not very good, the error corresponds to 1 nanosecond. It is 1/10 and the product can pass. But when the speed is increased to 1 Gbps, it corresponds to 1 nanosecond. If the test technology and scheme stay at 1 nanosecond, the proportion of errors is 50%. Half of the errors are of course fatal. Obviously, the old technology and methods make the space for making mistakes less.
Second, the efficient test plan requires high precision and high efficiency of the test, grasping the problem and providing the corresponding solution to find the underlying cause. Perhaps for the user, computer restart is just a bad experience. But the company that produces the computer will find the problem through the test plan and avoid it in the next stage. Tektronix introduced new TLA7S16 and TLA7S08 serial analyzers for testing and validating PCIe 1.0 and 2.0 designs in September 2007, providing detailed PCIe 2.0 protocol information and cross-bus analysis capabilities to see three layers of conditions. , namely the physical layer, the data link layer, and the transaction layer. If the command sent is to take the number 2, but takes the number 1, this development error can be seen by many protocol analyzers. But where is the root of the change from 2 to 1? Tektronix's solution is to be able to connect, map, and see that 2 becomes 1 in the data layer, and then find the root of 2 to 1 in the physical layer. These root causes may be bit errors (such as overshoot), poor power management, or reflections on the board design. In this way, the engineer can change the board, line width and line spacing according to his own experience.
Finally, the test instrument has reached the speed of 3G, 6G, or even 10G. It is true that 20G is better than 10G. "But in addition to the indicators, it depends on how many things 20G and 10G do. The figures may be a view of selling or comparing shallow customers to the instrument," Sun Zhiqiang said. Tektronix saw the impact of engineers behind the numbers and aims to meet customer requirements through its full range of hardware metrics.
It can be asserted that in the future electronic information industry, high-speed serial bus must be the mainstream of speed transmission solutions. Since 2006, Tektronix has been promoting a number of "digital new world" strategies, the most important of which is high-speed serial testing. Sun Zhiqiang, D&M market development manager for Tektronix Asia Pacific, said that there are six challenges in high-speed serial testing, namely signal integrity, receiver testing, serial data network and link analysis, compliance testing, system integration and data link analysis.
From production, high-speed serial testing can be divided into three parts: design, commissioning and inspection, and conformance testing. In the design phase, engineers can use the relevant simulation software to evaluate their own designs; and the real meaning of testing begins with the second phase, engineers need to use a variety of instruments to debug and test the system; at the same time, in order to meet the specifications of an application Conformance testing is also essential to achieve barrier-free interconnection of products between various manufacturers. However, because the conformance test belongs to the verification process, it can only measure whether the indicator meets the requirements, and cannot provide the fault and the improvement, so it cannot replace the debugging process.
From the perspective of the entire system, high-speed serial testing can be divided into: source, receiver and interconnect testing. The source test is a description of the source of the high-speed serial bus. It is usually measured by various indicators such as jitter, eye diagram and level. The receiver test is more about the receiver's receiving capability. The interconnect is more concerned. Connect the source and receiver traces, and other media characteristics (including impedance and crosstalk, etc.).
Six major challenges
Signal integrity is for source-side testing. The test specifications for each serial bus source are different, but the main considerations are basically the same. Among all the parameters, jitter and time offset are almost the same for all standards. An eye diagram is a method of characterizing the macroscopic characteristics of a serial signal, looking at the intersection of the transmission quality of the signal and the upper and lower deformations. The requirements for the eye diagram are just like the human eye. It should be clean and beautiful, that is, the upper and lower deformation noise should be small, the finer the better, the smaller the jitter.
Conformance testing is a bit like a "stamped" test. It is a test after the other five aspects are done to ensure that the interface can connect to any standard interface device in the world.
Serial data networks and links include impedance and link analysis of serial data network boards. The ideal impedance is a constant. For example, when light travels, the air does not reflect or refract, but through the window, it refracts and reflects. High-speed serial is typically a 100 ohm serial impedance, but if done poorly, it is 85 ohms or 82 ohms. In addition, comprehensive serial link analysis of noise and jitter is required. According to Sun Zhiqiang, Tektronix is ​​the only and the first to provide complete serial data link analysis on sampling oscilloscopes while observing jitter noise and bit errors.
"Two or three years ago, we didn't care about receiver testing," Sun Zhiqiang told Electronic Engineering World. Because Tektronix believes that the transmitter is tested well, the margins behind it are sufficient to make the signal received by the receiver intact. However, with the increase of speed and complexity, many signals of 1 become 0.8, 0.9 or even 0.7 at the receiving end, and once it becomes 0.5, it is impossible to determine whether the transmitted signal is 1 or 0, so high-speed serial test. Includes receiver testing. This requires the test instrument not only to be convenient to use, but also to generate as many error signals as possible and deliberately issued to judge the performance of the receiver. Traditional receiver testing often requires many sources such as noise sources, jitter sources, and basic data sources.
The four major challenges mentioned earlier exist in the physical layer, and the challenges of the data link layer come from two aspects: system integration and data link analysis. If the physical layer is good in all four aspects, you need to check the data link layer. This requires not only the performance of the test instrument, but also the multi-layer observation, that is, the oscilloscope (see physical layer) and the logic analyzer (see The data layer) is linked to a piece, and Tektronix introduced this concept five or six months ago. The physical layer mainly sees the physical analysis and simulation analysis of the serial link, while the data link layer mainly analyzes the data and protocols. The TAK7S16 and TLA7S08 serial analyzers introduced by Tektronix in September 2007 are implemented. An ideal cycle from equipment to test to design.
Of course, the six major challenges of high-speed serial testing are the customer's problems and challenges in the development process, which can be quickly resolved; and there are early preparations for problems that may be encountered tomorrow or the day after tomorrow. Rather than the challenge of engineers, it is the challenge of the test company, and the challenge of the test company comes from the challenge of using test instruments. Sun Zhiqiang said that Tektronix aims to help testers achieve easier design and production. , the concept of "Enabling" often mentioned in recent years.
How to meet the final needs
If you look for a typical application for high-speed serial technology, you can find it with a typical computer system. Such as PCI Express, HDMI3D, DisplayPort, SATA2 generation 3 generation, USB3.0, etc., applications such as high-speed DVR, communication, 10G Ethernet and so on. Sun Zhiqiang said that Tektronix's mission is to cooperate well with the organization and core companies of these programs.
The difference between applications and standards determines the different needs of customers. So how do high-speed serial test systems, which are already very complex, meet these diverse needs?
Testing needs of test centers, system vendors, modules, and chip vendors are the same - time is efficient, but the focus is not the same, so the choice of instruments is not the same. Production companies are more concerned with price, because time is money, and also requires test equipment to do 10 minutes in 1 minute. For example, the Tektronix DPO Series oscilloscope can take 100 seconds to capture 100 waveforms, while the DSO (Digital Storage Oscilloscope) series can take 60 seconds or 2 minutes. Efficiency, fairness, reliability, and repeatability are critical to the test center. If the same test process, the same personnel test, the test results of the instrument at 8 o'clock in the morning and 2 o'clock in the afternoon are different, which means that the temperature has a great influence on the instrument and the repeatability is not high. The requirements for system chips and module manufacturers are different.
A variety of needs are driving the advancement of technology, and no technology has an absolute competitive advantage. From the initial serial to the subsequent parallel, to the current high-speed serial, however, the basic principle of "higher parallel communication at the same frequency" is no problem. So how many challenges are there after the "six major challenges"? And let us wait and see!
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