ADI's AD9547 is a dual / quad input network clock generator / synchronizer that can provide synchronization for many systems including synchronous optical networks (SONET / SDH). The input reference frequency is from 1 kHz to 750 MHz, frequency monitoring is 1 ppm, and the output Frequency up to 450MHz, mainly used in network synchronization, OC-192 SONET / SDH clock, wireless base station, controller, wired infrastructure equipment and data communication. This article introduces the main features of AD9547, functional block diagram, detailed block diagram, output synchronization block diagram and evaluation Board circuit diagram and evaluation board bill of materials.
AD9547: Dual / Quad Input Network Clock Generator / Synchronizer
The AD9547 provides synchronizaTIon for many systems, including synchronous opTIcal networks (SONET / SDH). The AD9547 generates an output clock that is synchronized to one of two differenTIal or four single-ended external input references. The digital PLL allows for reducTIon of input time jitter or phase noise associated with the external references. The AD9547 continuously generates a clean (low jitter), valid output clock, even when all references fail, by means of digitally controlled loop and holdover circuitry. The AD9547 operates over an industrial temperature range of −40 ℃ to + 85 ℃.
AD9547 main features:
Supports Stratum 2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Automatic / manual holdover and reference switchover
2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent single-ended inputs
Input reference frequencies from 1 kHz to 750 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as a single differential LVDS / LVPECL output or as 2 single-ended CMOS outputs
Output frequencies up to 450 MHz
20-bit integer and 10-bit fractional programmable feedback divider
Programmable digital loop filter covering loop bandwidths from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
64-lead LFCSP package
AD9547 application:
Network synchronization
Cleanup of reference clock jitter
SONET / SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient control
Stratum 3E and Stratum 3 reference clocks
Wireless base stations, controllers
Cable infrastructure
Data communications
Figure 1. AD9547 functional block diagram
Figure 2. AD9547 detailed block diagram
Figure 3. AD9547 output synchronization block diagram
Figure 4. Circuit diagram of the AD9547 evaluation board (1)
Figure 5. Circuit diagram of the AD9547 evaluation board (2)
Figure 6. Circuit diagram of the AD9547 evaluation board (3)
AD9547 Evaluation Board Bill of Materials (BOM) see:
AD9547: Dual / Quad Input Network Clock Generator / Synchronizer
The AD9547 provides synchronizaTIon for many systems, including synchronous opTIcal networks (SONET / SDH). The AD9547 generates an output clock that is synchronized to one of two differenTIal or four single-ended external input references. The digital PLL allows for reducTIon of input time jitter or phase noise associated with the external references. The AD9547 continuously generates a clean (low jitter), valid output clock, even when all references fail, by means of digitally controlled loop and holdover circuitry. The AD9547 operates over an industrial temperature range of −40 ℃ to + 85 ℃.
AD9547 main features:
Supports Stratum 2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Automatic / manual holdover and reference switchover
2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent single-ended inputs
Input reference frequencies from 1 kHz to 750 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as a single differential LVDS / LVPECL output or as 2 single-ended CMOS outputs
Output frequencies up to 450 MHz
20-bit integer and 10-bit fractional programmable feedback divider
Programmable digital loop filter covering loop bandwidths from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
64-lead LFCSP package
AD9547 application:
Network synchronization
Cleanup of reference clock jitter
SONET / SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient control
Stratum 3E and Stratum 3 reference clocks
Wireless base stations, controllers
Cable infrastructure
Data communications
Figure 1. AD9547 functional block diagram
Figure 2. AD9547 detailed block diagram
Figure 3. AD9547 output synchronization block diagram
Figure 4. Circuit diagram of the AD9547 evaluation board (1)
Figure 5. Circuit diagram of the AD9547 evaluation board (2)
Figure 6. Circuit diagram of the AD9547 evaluation board (3)
AD9547 Evaluation Board Bill of Materials (BOM) see:
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