LSI packaging market trends
The world's electronic information equipment market, be summed up by LSI package, as shown, total deliveries increased 1 turn in 2003, followed by increases along by the year 2005 is expected to reach in 2001 1.5 times the size.
In terms of packaging form, surface mounts represented by SOP ( Small Outline Package ) and QFP (Quad Flat Package ) are the mainstream and account for an overwhelming proportion. This trend has remained almost unchanged in 2005 . In terms of growth rate, 2005 is expected to increase by 50% over 2001 .
In contrast, DIP ( dual in-line package ) represented by pin-inserted packages accounted for only 10% of the total in 2002 , but the trend of gradual decline has continued, and will shrink to about 6% by 2005 . On the other hand, in a BGA (ball grid array) or CSP (chip scale package) as the representative of area array packages show a greater growth rate after 2002, the year 2005 will be three times the size of 2001, reaching More than 10% of all packages .
In addition to the above, it is expected that a significant increase will be in the form of 3D SiP packaging ( system packaging ) . In 2001 it was almost impossible to get statistics, but in 2005 it will reach 5 times the scale of 2001 , accounting for more than 3% of the entire package .
Picture 1 Â Variation and forecast of demand for multiple packaging forms
Picture 2 Â Changes in LSI packaging
LSI packaging technology evolution
Overall analysis
Thermoelectric system and improve performance, especially high-frequency high pin count demand, to promote traditional packaging technology to package the peripheral area array package pin, the pin is inserted into the surface-mount type progress, and then from the SCP (Single Chip packaging ) progressed to SiP . The new packaging form comes out, but it does not mean that the past packaging will be replaced immediately and disappear. For quite some time, the past packaging form still dominates. Even today, SOP and QFP in peripheral pin packages still account for the majority. The technical changes of various packaging forms are shown in Figure 2 .
Early DIP package pins are located on both sides of the IC , and are mostly used for devices with less than 64 pins , including various memories and microcontrollers. After the surface mount pins is divided into both sides of the SOP and IC pinout around the IC in the LCC (leaded / leadless chip carrier) and QFP form. SOP is used for devices with less than 64 pins , including TSOP ( Thin Small Outline Package ) , TSSOP ( Thin Miniature Outline Package ) , SSOP ( Miniature Outline Package ) , SOJ ( Small Outline J Type Lead Feet ) etc. QFP is commonly used in high-pin-count packages for ASICs , logic ICs, and various mid- and low-end devices, with pin-count ranges of 36-208 and 212-304 .
In order to cope with the increasing number of IC pins and the trend of light and thin devices, the BGA package form that uses solder balls to connect chips to circuit boards began to develop after the 1990s , and further developed FPBGA ( fine pitch BGA) , CSP , FCP (flip chip package), a WLP (wafer level package), the TCP (Tape package) as well as with a variety of packaging techniques that combine multiple satellites wafer MCP (multi chip package), a SiP other high-end packaging technology In order to meet the needs of CPU , PC chipset, graphics chip, FPGA , ASIC chip high efficiency, high speed, high integration, high I / O number, environmental protection, power saving and so on.
BGA package is suitable for high-pin-count IC products, mainly for SoC , graphics chipset, FPGA , wireless communication and other application chips, especially the I / O number exceeds 300. The traditional pin-inserted packaging method has been unable to meet the demand. BGA package The market is gradually expanding.
CSP is suitable for low-pin-count ICs . The IC area after packaging is no more than 1.2 times the size of the bare chip . The advantage of CSP is that it is small and thin, and can provide good heat dissipation. It is mainly used for memory products such as DRAM , SRAM , Flash and so on. In particular , the new device DDR â…¡ extended from SDRAM is ultra-high speed, small size, and high capacity development. With CSP as the standard package, the traditional TSOP package can no longer support its basic architecture, and it must transform to CSP .
Three major technology trends
Flip Chip technology is a typical wafer-level package, a chip bumps (Bump) and the substrate (Substrate) in place of the wire bonding connection (wire bonding) technique, for I / O number of the above product in 1000, its advantage lies in its ability Significantly improve the electrical and thermal performance of the product. Flip Chip is suitable for high-pin-count, high-speed, multi-function devices, such as high-performance MCU , MPU , ASIC , RF , high-end DSP , SoC , graphics chipset with communication, Internet access, wireless transmission, digital image processing, GPS function Wait, the application level is very wide. But its entry barrier is high so that the winner of the technology can take advantage of the market.
The traditional IC packaging process is to cut the wafer into a bare chip and then test the package, and WLP simplifies the above process, after directly packaging and testing on the entire wafer, and then cutting into a single die There is no need to go through any packaging steps in the middle, which significantly reduces the size of the IC and greatly reduces the packaging cost. The advantage of WLP is also: because there is only solder balls between the chip and the circuit board, the circuit transmission path can be shortened, the inductance and capacitance can be reduced, so the probability of current loss and electromagnetic wave interference can be effectively reduced, thereby improving the working efficiency of the circuit ; Due to the lack of plastic or ceramic packaging on the outside of the IC , the heat loss generated by the IC chip during operation can be directly dissipated from the back of the chip by heat conduction and heat radiation, which can effectively solve the heat dissipation problem of the mobile electronic device. At present, portable electronic products such as mobile phones, PDAs , notebook computers, digital cameras and MP3 players, all benefit from WLP technology. Applications are mainly concentrated in three areas, namely low I / O count ICs ( such as analog, radio frequency, power amplifier, power supply devices ) , memory (EEPROM , Flash) and passive components. Future market development In addition to the continuous increase in low-pin-count devices, the application of high-speed devices such as memory will also continue to develop.
The current development of SoC is facing bottlenecks and challenges. For example , the cost of a 0.13 micron mask is as high as more than 1 million US dollars. On the other hand, the narrower the process pitch, the greater the gate leakage current, and the difficulty of high speed after miniaturization. SiP still maintains independence between components in the package, so it can avoid the difficulties in the process of integrating analog and digital circuits in SoC design, reduce the complexity of circuit design, shorten the design time, and ensure the yield rate. Therefore, when the SoC technology is not yet mature, SiP has good development opportunities and will become the first choice of many system manufacturers.
In the past, the SiP technology was still based on the 2D form in which multiple bare chips combined into a system were placed on the same substrate plane , and the way of connecting the IC to the substrate was wire bonding, flip chip, and automatic tape and reel bonding. (Tape Automated Bonding , TAB) and other technologies, this type of packaging still has various shortcomings such that the circuit transmission path is too long and the packaging volume is too large. The previous MCM ( multi-chip module ) package is a SiP case in the form of a 2D plane . In MCM , multiple ICs are placed on the same substrate plane, and then interconnected by wire bonding. However, in addition to the above-mentioned short transmission path and difficulty in shrinking the packaging volume, this type of packaging also has difficulty in controlling the yield. In order to improve the above-mentioned shortcomings, currently SiP is gradually moving towards stacking and packaging chips in 3D . There are two types of 3D stacked packages, one is to directly stack the bare chips and connect them to the substrate, and then package (chip stacked) , the other is to stack multiple packaged chips and then combine them together (package stacked ) . The former packaging method can only overlap up to four layers of bare chips, and it is difficult to test. At present, the 3D form of SiP is still mainly based on the latter's package stacked . There are also many, and can meet the needs of light and thin.
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