Microprocessors and application-specific integrated circuits (ASICs) demand low-voltage, high-current power supplies. These power supplies must meet strict output voltage deviation requirements, especially during load transient events. Designing and testing these power supplies can be complex, making it challenging to ensure they meet all specifications.
This article explores key questions about load transient testing and provides practical methods for simplifying the process under demanding conditions.
To design a reliable power supply, it's essential to understand the transient parameters involved. Common parameters include:
- The magnitude of the load step (in amps or as a percentage of full load)
- The minimum load during transients (which can sometimes be zero)
- The rate at which the load changes (typically expressed in amps per microsecond)
- The maximum allowable voltage deviation
- The estimated recovery time after the transient
Figure 1 shows how these specifications are typically defined.
Figure 1: Graphical representation of load transient measurements.
Once you have a clear understanding of these parameters, designing a power supply that meets your needs becomes more straightforward. However, testing according to these specifications is often a major challenge. For example, an output voltage of 1V with a 100A load step and a conversion rate of 1000A/μs is not common. In most cases, the limiting factor is the parasitic inductance between the power supply and the load. In real-world systems, power supplies are usually located close to the load to minimize this inductance.
There are several approaches to testing load transient response, each with its own advantages and limitations. In this article, I’ll compare five common options: external electronic loads, external transient boards, FET slammers, onboard transient generators, and socket-based transient testers.
External electronic loads are widely used due to their ease of use and flexibility. Most models allow users to set current levels and transition times easily. However, they are limited by the wiring and the actual load capabilities, which can restrict the achievable slew rate.
External transient boards offer better performance in terms of slew rate, but this comes at the cost of reduced flexibility. Depending on the design, they may be limited by maximum current, heat dissipation, or the board’s own slew rate. Additionally, since they are external components, the wiring often becomes the main bottleneck for achieving high-speed transients. They also require configuration for each test setup.
FET slammers provide a fast and simple way to achieve high-speed transients. A metal-oxide semiconductor field-effect transistor (MOSFET) is connected from drain to source via a resistor or directly to the power supply output, with the gate controlled by a function generator. The minimal external wiring reduces parasitic inductance significantly.
While FET slammers can produce high slew rates, they are difficult to control and repeat consistently. They may require modifications to the PCB (see Figure 2), and measuring the actual load step current can be inaccurate due to the lack of direct measurement tools.
Figure 2: Example of a PCB modified for FET slammer use.
For high-current, high-speed transient testing, an onboard transient generator is a practical solution that can be tailored to specific load transient requirements. However, it adds to the cost and space of the system. It can also be time-consuming to perform multiple tests with different configurations.
The design of an onboard transient generator can vary from simple setups using a 555 timer and FET to more advanced designs that use multi-stage switching and smaller, faster FETs to achieve a slew rate of 1000A/μs. Figure 3 shows an example of a complex design.
Figure 3: A complex onboard transient generator design.
The last option involves using a processor socket and a dedicated transient tester. This method is the most expensive, as both the tool and the PCB add significant costs. However, it offers the highest accuracy for specific processor or ASIC requirements. Many manufacturers develop such tools to ensure proper test conditions are met.
Table 1 summarizes the key differences between the various transient testing methods.
Table 1: Comparison of different transient test methods.
Load transient testing is a critical part of power supply design and validation. Parasitic inductance in the test setup can significantly affect the ability to achieve the desired slew rate. By using one of the methods described above, engineers can overcome these challenges and improve the reliability and performance of their power supplies.
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