Analysis of the turning point in the current (Is) waveform from the source of the flyback switching MOSFET.
In power supply design and debugging, engineers often encounter unclear or ambiguous waveforms. This article dives into the analysis of the Is waveform in a flyback converter to help understand some common issues.
One common issue is a spike at the beginning of the Ids current waveform when the MOSFET turns on. As shown in the red circle in the figure below, this spike is not unusual but can be confusing for many. What causes it, and how can it be minimized?
It’s well known that this spike occurs during the turn-on phase of the MOSFET. In a flyback circuit, the Ids current path goes through the primary winding of the transformer and back to Vbus via the MOSFET. Normally, the primary inductance would cause a linear rise in current. However, due to the distributed capacitance between the turns of the primary winding (denoted as C in the diagram), a high-frequency path is created at the moment the MOSFET turns on. This results in a very short but sharp current spike.
From this analysis, we can conclude that the spike is caused by the parasitic capacitance of the primary winding. To reduce this effect, it's important to optimize the winding structure—such as increasing the spacing between layers, using single-layer windings where possible, and reducing the number of turns. A larger Ae (effective area) in the transformer design can also help, as it reduces the number of turns and thus minimizes inter-winding capacitance.
Additionally, techniques like the sandwich winding method can improve coupling and reduce leakage inductance, which in turn helps minimize the peak current. However, it's important to note that parasitic capacitance cannot be completely eliminated, so the spike will always exist to some degree. While the oscillation caused by this spike may affect EMI performance, its impact on the system is generally minimal unless the spike is excessively large, which could potentially trigger false overcurrent protection in the IC.
To prevent this, most power ICs include a 200nS–500nS LEB (Low-Energy Burst) time delay to avoid false triggering. This is a standard feature in many modern power management ICs.
Another common waveform anomaly is a dip in the Is current waveform when the MOSFET turns off, as seen in the red circle in the figure below. Why does this happen, and how can it be improved?
Before diving into the explanation, let's compare the drain current (Id) and source current (Is) waveforms. The measured Id waveform looks like this:
The measured Is waveform is as follows:
As you can see, the Id is greater than Is. This is because Is includes a negative current component, specifically the Cgs discharge current. This explains the inflection point observed in the Is waveform.
So, to improve this, one approach is to adjust the MOSFET model or optimize the gate drive characteristics. But another question arises: why does the Id waveform show a negative current when the MOSFET turns off, as shown below?
When the MOSFET turns off, the energy stored in the leakage inductance is transferred to the MOSFET's output capacitance (Coss). This causes a voltage spike on Vds, which then reverses after reaching its peak. During this reverse discharge, a negative current appears in the Id waveform. This phenomenon is normal and expected in flyback converters, but it's important to manage it to avoid excessive stress on the MOSFET and potential EMI issues.
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