S3C2410 initialization code mainly involves the configuration of the main modules of the system, the establishment of the operating environment, the system clock, MMU and other modules configuration, following the order of execution are analyzed in each part:
l program entry: (ResetHandler)
At the beginning of the program, some of the first operations are mainly to ensure that the initialization program can run smoothly. Therefore, it mainly includes shutting down the WDT, interrupts, and configuring the phase-locked loop.
l Configure the memory interface
The memory interface is the basic guarantee for correct data access. Here, the memory interface register set starting from 0x48000000 in the SFR register is mainly configured to ensure that each bank has the correct bit width, wait type, and timing parameters. If there is no special requirement, the default timing parameters can be used.
l initialize the stack
ARM has 6 operating modes. It must provide independent stack space for each mode. Before the stack is set, it cannot call C functions. Arm's stack mode is decremented from the high address, we can set the stack's first address at 0x33ff8000, followed by FIQ, IRQ, Abort, Undef, and SVC in descending order, where the SVC and User modes are not distinguished. The stack size can generally be modified in the header file or the current file.
l Initialization of the operating space
This code mainly accomplishes two functions. One is to move RW data to RW space (when we generate ROM image, RW data is after RO data), and the other is to initialize the ZI data segment. Of course, the premise of this code is that the running environment of the code is only a standard two-stage type: a section of RO space and a section of RW space; and no compiler-linked library (__main) is called at the entry of the C program. The latter already provides the corresponding functionality and supports more complex runtime environment definitions (using SCF files).
L__rt_lib_init
In the context of ADS 1.2, if the compiler's link library (__main) is not invoked at the C entry, the function is called at the beginning of the C program to initialize the runtime library to guarantee certain libraries provided by ADS. The function can be called normally.
lMMU initialization
The 2410 MMU supports Level 1 & Level 2 address mapping. In our current application, the address mapping of Level 1 secTIon mode is used. The size of a secTIon is 1M, which means that the transition from a logical address to a physical address is such a process. : A 32-bit address, the upper 12 bits determine the index of the address in the page table, the content of this index determines the physical secTIon corresponding to the logic secTIon; the lower 20 bits determine the offset of the address in the section (index ).
Therefore, the address space from 0x0 to 0xffffffff can be divided into 0x1000 (4K) sections, and the size of each item in the page table is 32 bits. Therefore, the size of the page table is 0x4000 (16K). The page tables of all sample programs are stored uniformly at address 0x33ff8000.
The contents of each page table entry are as follows:
31 20 19 12 11 10 9 8 5 4 32 1 0
Section corresponding physical address NULLAP0Domain1CB10
Note: The lowest two digits (10) are the identification of the section tab.
AP: Access Permission, distinguishing read-only, read-write, SVC & other modes.
Domain: Each section belongs to a Domain, one has 16 Domains, and the attributes of each Domain are controlled by the R15 register of CP15. In all the sample programs, only two Domains are included, one is the space below the SFR address (including the SFRs), and it is accessible; the other is the space above the SFRs and cannot be accessed.
C, B: These two determine the cache&write buffer attribute of the section, which is closely related to the purpose of the segment (RO or RW). Different uses do different settings.
CB specific meaning
00 no cache, no write buffer, any read and write to the memory are reflected on the ASB bus. The CPU needs to wait during the memory operation.
01 No cache, write buffer, read directly reflected on the ASB bus. Write operation The CPU continues to write data after writing to the write buffer and ASB operation is performed by the write buffer.
10 has a cache, write mode, read operations first consider the cache hit; write directly write data to the write buffer, if there is a cache hit, then update the cache.
10 has a cache, write back mode, read operation first consider the cache hit; write operation also consider the cache, if the hit, then only modify the cache, and the cache corresponds to a half row of dirty bit set; if miss, write write buffer , trigger ASB bus operation.
Although the MMU only uses a linear transfer of logical address to physical address (value does not change), because the MMU can introduce cache & write buffer, system performance has greatly improved!
Configure the clock ratio and reset the PLL
The 2410 has three internal clocks: FCLK, HCLK, PCLK, for the CPU, AHB bus, and
APB bus use, in order to reduce power consumption, generally choose a reasonable ratio of 1:2:4 cycle ratio. At the same time, the PLL is configured as the operating environment clock, which generally reaches a maximum of 202M.
IO initialization
The IO port is configured as a corresponding function option, and the corresponding LED lamp is generally lighted.
Interrupt initialization
The 2410 memory space does not have a remap mechanism and should interrupt the entry clock at zero address. Therefore,
The broken service mechanism can be described as follows:
First of all, no matter what kind of startup method you use, you must make sure that the code segment is at the 0x0 address of the memory:
b ResetHandler
b HandlerUndef ;handler for Undefined mode
b HandlerSWI ;handler for SWI interrupt
b HandlerPabort ;handler for PAbort
b HandlerDabort ;handler for DAbort
b. ;reserved
b HandlerIRQ ;handler for IRQ interrupt
b HandlerFIQ ;handler for FIQ interrupt
Except for ResetHandler, all other items are defined by the following macro code:
HandlerFIQ HANDLER HandleFIQ
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel
Sub sp,sp,#4 ;decrement sp(to store jump address)
Stmfd sp! ,{r0};PUSH the work register to stack
Ldr r0,=$HandleLabel ;load the address of HandleXXX to r0
Ldr r0,[r0] ;load the contents
Str r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stack
Ldmfd sp! ,{r0,pc} ;POP the work register and pc(jump to ISR)
MEND
The meaning of this code is to assign the contents of the interrupt vector table to the PC pointer through the stack (eg HandleFIQ is the address where the FIQ service program entry address is stored), and the natural program jumps to the corresponding entry address.
It can be seen that the interrupt vector table stores the entry address of each interrupt service program. It is used to be loaded, not executable code. For consistency, all sample programs place the interrupt vector table at the address starting from 0x33ffff00, and are arranged in order according to the entry address.
It should be noted that if various modes of service programs are defined in the C language, the types must be defined with __irq to ensure that they are returned correctly.
Initialize the serial port
Uniform serial port selects UART0, the mode uses 115200, 1bit STOP, No Parity.
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