Radio Frequency Identification (RFID) is a non-contact automatic identification technology that allows for the automatic recognition of objects and the retrieval of associated information through radio frequency signals. An RFID system typically consists of application software, RF tags, and a reader [1]. Compared to low-frequency RFID systems, ultra-high frequency (UHF) RFID systems operating in the 860–960 MHz range offer advantages such as longer read distances and faster reading speeds, making them a major focus in global RFID development [2]. The design of the RFID reader plays a critical role in the overall system, and there are multiple approaches to its implementation. Field Programmable Gate Arrays (FPGAs) are widely used due to their ease of development, static reprogramming capability, and dynamic online programming features, making them one of the most popular programmable ASICs today [3]. Many companies that produce RFID products use their own proprietary standards, but several international standards exist, including ISO/IEC 11784, ISO/IEC 14443, ISO/IEC 15693, and ISO/IEC 18000. Among these, ISO/IEC 14443, ISO/IEC 15693, and ISO/IEC 18000 are the most commonly adopted [4]. This paper presents the design of an RFID reader operating at 915 MHz based on the ISO/IEC 18000-6 Type B protocol.
The hardware of the RFID reader is divided into three main modules: the FPGA digital signal processing module, the MCU and human interface module, and the RF transceiver module. A block diagram of the system is shown in Figure 1. The FPGA module is responsible for implementing the baseband data encoding and decoding specified by the ISO/IEC 18000-6 Type B protocol. The MCU and human interface module handles user interaction, such as command control and data display. The RF transceiver module processes the UHF signals from the front end.
1.1 FPGA Digital Signal Processing Module
The FPGA digital signal processing module includes a clock divider, FIFO buffer, Manchester encoder, CRC generator, FM0 decoder, serial-to-parallel converter, and a frame controller. Its block diagram is illustrated in Figure 2. The internal workflow of this module involves both sending and receiving operations. In the sending process, data from the MCU is received via a parallel interface, stored in the FIFO, converted to serial format, and then passed through the CRC module to generate a 16-bit checksum before being Manchester-encoded. The encoded data is then sent to the RF transceiver. On the receiving side, the RF transceiver sends a baseband signal to the FPGA, where the frame header is detected, followed by FM0 decoding. The decoded data is converted back to parallel format, checked using CRC, and either sent to the MCU or discarded if an error is detected.
1.2 MCU and Human Interface Module
This module is built around the C8051F020 microcontroller, which interfaces with various peripherals such as an LCD, PS/2 keyboard, UART, and JTAG. It manages the coordination of the entire system, initializes the FPGA, controls the reader commands, processes card data, implements anti-collision algorithms, drives the display, and stores card information in EEPROM. The block diagram of this module is shown in Figure 3.
1.3 RF Transceiver Module
The RF transceiver module can be implemented using either discrete components or a pre-built RF transceiver chip. Due to the complexity and long development time of the former approach, the latter was chosen. The TR1000 chip from RFM is used, offering high stability, small size, low power consumption, and cost-effectiveness. It supports ASK modulation for communication from the reader to the tag and backscatter modulation for the reverse direction, which can be demodulated as ASK.
2 Software System Design of the Reader
The software follows a modular and structured programming approach, with the FPGA configured by the microcontroller during initialization. C language was selected for its readability, portability, and compatibility with the MCU. The software is divided into three main parts: the card reader program, the anti-collision algorithm, and the serial communication module.
2.1 Read and Write Card Procedures
The card reader/writer program implements baseband signal encoding and decoding according to the ISO/IEC 18000-6 Type B protocol. The flowchart of the program is shown in Figure 4. Upon power-on, the system initializes the microcontroller, ports, LCD, timer, FPGA, and interrupts. It then waits for a command from the host or keyboard. If a multi-card operation is detected, it enters the anti-collision routine; otherwise, it proceeds with reading, writing, or other operations. If successful, the data is returned to the host and displayed on the LCD; otherwise, an error message is shown.
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