Distributed amplifiers are known for their wide frequency range and high gain, making them essential in many microwave and RF applications. Historically, their design relied heavily on transmission lines for input and output matching. In 1948, Bill Packard, a co-founder of Hewlett-Packard, introduced a vacuum tube amplifier based on distributed design principles in his paper. With the advancement of gallium arsenide (GaAs) microwave monolithic integrated circuits (MMICs), various amplifier designs have emerged to improve efficiency, output power, and noise performance. However, distributed amplifiers remain a key solution for broadband applications such as optical communication.
At Johns Hopkins University, since the early 1980s, an MMIC design course has been offered, allowing students to access TriQuint’s production line. A classic example from this course is a distributed amplifier designed by Craig Moore, who served as a teaching assistant from 1987 to 2003. This design was even tested under low-temperature conditions, showing reduced noise figures at liquid nitrogen temperatures. The original design used TriQuint’s 0.5μm GaAs MESFET process, which had slightly lower gain compared to newer 0.5μm GaAs PHEMT-based circuits. In 2006, a new version using 0.5μm GaAs PHEMT was introduced, along with other examples. This article will explore the design methodology and simulation results of a wideband amplifier.
Figure 1 shows the schematic of a distributed amplifier using microstrip transmission lines. The circuit injects an input signal into a set of active devices through a broadband transmission line, while another parallel line collects and combines the outputs. Each stage contributes similar gain, but the overall gain is spread across a wide frequency range. Unlike cascaded amplifiers, where total gain is the product of individual gains, distributed amplifiers sum the gains of each stage. When using lumped components to approximate transmission lines (as shown in Figure 2), the shunt capacitance is replaced by transistor parasitic capacitance, forming a low-pass filter whose cutoff frequency depends on the transistor size. Thus, the transistor's size directly affects the upper operating frequency.
Designers must consider multiple factors, including the number of stages, device size, process type, and DC biasing. More stages increase the gain-bandwidth product but also introduce more complexity. Once the transistor size is chosen, simulation tools like ADS can optimize parameters such as gain, reflection coefficient, output power, and noise figure.
In the Craig Moore design, an enhanced PHEMT was used for its single positive voltage supply requirement. The circuit aimed to match the performance of TriQuint’s 0.5μm GaAs MESFET design, using a 3-stage topology with a 3.3V supply for battery-powered applications. Adjustments in voltage and current allow flexibility for different customer needs. Simulations showed that even at 1.5V and 14mA, the gain loss was only 2dB, with minimal performance variation when the drain current changed between 14–35mA. Linear simulations with ADS were used to determine optimal inductance and PHEMT size for maximum gain and matching.
Through ideal simulations, the design used 6×30μm enhanced PHEMTs, adding extra matching components to the MESFET drain to balance output and input capacitances. This ensured symmetry in the input and output transmission lines, maintaining consistent phase delay. The article also compared this symmetric approach with an alternative method involving leakage capacitors and asymmetrical gate-drain configurations. For a simple 3-stage PHEMT design, the phase difference was small, so an asymmetric configuration was sufficient. However, if the phase shift is large, the symmetric scheme becomes necessary.
Realistic simulations replaced ideal components with TriQuint’s models for inductors, resistors, capacitors, and interconnects. Figure 3 shows the final amplifier’s gain, matching, stability, and noise performance. The design used a 30mA, 3.3V bias to keep power consumption under 100mW, balancing output power and third-order intermodulation distortion. Figure 4 displays the layout, including two test structures: one for the 6×30μm enhanced PHEMT and another for a common 6×50μm depletion PHEMT.
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